Field of the invention
The present invention relates to a method for fabricating a trench capacitor for a dynamic random access memory (DRAM) memory cell. A trench is formed in a substrate and a lower capacitor electrode that adjoins a wall of the trench is provided in a lower trench region. A storage dielectric and an upper capacitor electrode are than produced.
In dynamic random access memory cell configurations, it is known to virtually exclusively use what are known as single-transistor memory cells. A single-transistor memory cell contains a read transistor and a storage capacitor. Information is stored in the storage capacitor in the form of an electric charge that represents a logic 0 or a logic 1. Actuating the read transistor via a word line allows the information to be read via a bit line. The storage capacitor must have a minimum capacitance for reliable storage of the charge and, at the same time, to make it possible to differentiate the information item that has been read. The lower limit for the capacitance of the storage capacitor is currently considered to be 25 fF.
Since the storage density increases from memory generation to memory generation, the surface area required by the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor has to be retained.
Up to the 1 Mbit generation, both the read transistor and the storage capacitor have been produced as planar components. Beyond the 4 Mbit memory generation, the area taken up by the memory cell was reduced further by using a three-dimensional configuration of the read transistor and the storage capacitor. One possibility is for the capacitor to be produced in a trench (see for example the reference by K. Yamada et al., Proc. Intern. Electronic Devices and Materials IEDM 85, pp. 702). In this case, a diffusion region that adjoins the wall of the trench and a doped polysilicon filling disposed in the trench act as electrodes for the storage capacitor. Therefore, the electrodes of the storage capacitor are disposed along the surface of the trench. In this way, the effective surface area of the storage capacitor, on which the capacitance is dependent, is increased with respect to the space taken up by the storage capacitor on the surface of the substrate, which corresponds to the cross section of the trench. Although there are limits on the extent to which the depth of the trench can be increased, for technological reasons, the packing density can be further increased by reducing the cross section of the trench.
However, one difficulty associated with the decreasing trench cross section is the increasing electrical resistance of the trench filling and the associated increase in the read-out time of the DRAM memory cell. Therefore, to ensure a high read-out speed as the trench cross section is further reduced in size, it is necessary to select materials with a lower resistivity as electrodes of the trench capacitor. It has to be possible for the materials to be deposited at very high aspect ratios that are typically used in trench capacitors. Many materials that are in principle suitable for this purpose experience a great amount of stress during deposition and subsequent heat treatment. The stress may lead to the metal layers flaking off, to an increase in leakage currents, for example as a result of stress in the capacitor dielectric, or even to the wafer fracturing.
U.S. Pat. No. 5,905,279 discloses a memory cell having a storage capacitor disposed in a trench and a select transistor, in which the storage capacitor has a lower capacitor electrode, which adjoins a wall of the trench, a capacitor dielectric and an upper capacitor electrode. The upper capacitor electrode contains a layer stack containing polysilicon, a metal-containing, electrically conductive layer, in particular made from WSi, TiSi, W, Ti or TiN, and polysilicon. The trench capacitor is fabricated by first forming the upper capacitor electrode in the lower trench region. Then, an insulating collar is deposited in the upper trench region, and next the upper capacitor electrode is completed. Alternatively, the method is carried out on an silicon-on-insulator (SOI) substrate which does not have an insulating collar, in which case the upper capacitor electrode, which contains a lower polysilicon layer and a tungsten silicide filling, is fabricated in a single-stage deposition method, in which the individual layers are deposited entirely in the trench.
However, the reduction in the series resistance of the upper capacitor electrode that can be achieved with this method is not yet satisfactory. Moreover, the method may also give rise to a very high level of stress, which can lead to considerable process engineering problems.